Processor Components

BIU (Bus Interface Unit)

The Bus Interface Unit is responsible for managing communication between the processor and the outside world (memory and input/output devices).

• Reads and writes data to memory.
• Controls the flow of instructions and data between the CPU and the system bus.
• Works in conjunction with the Execution Unit (EU), which executes the instructions.

L2 Cache

Level 2 Cache is a intermediate memory between L1 cache (faster and smaller) and main memory (RAM).

• It has greater capacity than L1, but is slower.
• Stores frequently used instructions and data.
• Reduces access in time to main memory.

Execution Unit (EU)

The Execution Unit is responsible for executing the operations sent by the processor. Its contains several subcomponents:

• ALU (Arithmetic Logic Unit): Performs mathemathical and logical operations (addition, subtraction, AND, OR, etc.).
• FPU (Floating Point Unit): Specialized in calculations with floating-point numbers.
• MMX/SIMD Units: Perform operations in parallel on multiple data (used in multimedia, graphics, and vector processing).
• Registers: Small storage areas within the CPU for storing temporary data and instructions in execution.
• Control Unit (CU): Interprets instructions and coordinates the flow of data between all CPU units.

L1 Instruction Cache

The **Level ONE Instruction Cache** is the first layer of cache memory dedicated **only for instructions**.

• Delivers instructions quicklyy to CPU.
• Small (typically 16–64 KB).
• Extremely fast close to the CPU registers.

L1 Data Cache

The **Level 1 Data Cache** is the first layer of cache memory dedicated **to data**.

• Stores values ​​and variables that are actively being used.
• It is also small and very fast.
• Works in parallel with the L1 Instruction Cache to optimize performance.

Word, Dword, and Qword

Word

• Means word (from the English word).
• In x86 its corresponds to 16 bits (2 bytes).
• Example: 0x1234 → occupies 2 bytes in memory.

Dword (Double Word)

• Means double word.
• In x86, it corresponds to 32 bits (4 bytes).
• This is the natural size of registers in 32-bit processors.
• Example: 0x12345678 → occupies 4 bytes in memory.

Qword (Quad Word)

• Means quad word.
• In x86-64, it corresponds to 64 bits (8 bytes).
• This is the natural size of registers in 64-bit processors. - Example: 0x1234567890ABCDEF → occupies 8 bytes of memory.

Summary Table

Note

• On some architectures, the term word may mean another size (for example, on ARM, it may be 32 bits).
• In x86, the convention is:
• Word = 16 bits
• Dword = 32 bits
• Qword = 64 bits

32 bits vs 64 bits

Dword in 32 and 64 bits

Origin

• The term dword means "double word".
• In x86, word = 16 bits → therefore dword = 32 bits.
• This originated in **32-bit processors (80386 and later).

In the 32-bit systems

• The main registers (EAX, EBX, ECX, EDX, etc.) are 32 bits.
• Therefore, the natural unit of operation is a dword.
• Example inn Assembly:

mov eax, dword ptr [var] ; load 32 bits (4 bytes) from memory

Number Systems

Binary (base 2)

• Uses only the digits 0 and 1.
• Each position is worth a power of 2.

Examples:

• 0b1010 = 10 in decimal
• 0b1111 = 15 in decimal
• 0b100000 = 32 in decimal

Decimal (base 10)

• This is the system we use in everyday life.
• Uses the digits 0 to 9.

Examples:

• 10 in decimal = 0b1010 in binary = 0xA in hexadecimal
• 255 in decimal = 0b11111111 in binary = 0xFF in hexadecimal

Hexadecimal (base 16)

• Use the digits 0 through 9 and the letters A, B, C, D, E, F
  (where A=10, B=11, …, F=15).

Example:

• 0xA = 10 in decimal = 0b1010 in binary
• 0xFF = 255 in decimal = 0b11111111 in binary
• 0x100 = 256 in decimal = 0b100000000 in binary

Quick Comparison

ASCII

What is it?

• ASCII stands for American Standard Code for Information Interchange.
• It is a table that associates numbers with characters.
• Each character is represented by a numeric value from 0 to 127 (7 bits).

Example conversion

Notes

• Printable characters range from 32 (space) to 126 (~).
• Values ​​from 0 to 31 are control characters (e.g., Enter, Tab, etc.).
• ASCII was the basis for other standards, such as ISO-8859 and UTF-8.

Registers

What are they?

• Registers are small areas of memory inside the CPU.
• Much faster than RAM or cache.
• They store temporary data, addresses, or instructions that the processor needs immediately.

Examples in x86 (16-bit → 32-bit → 64-bit)

General Registers

• Used for calculations and temporary storage

| 16-bit | 32-bit | 64-bit | Common Use | |---------|---------|---------|---------------------------|
| AX | EAX | RAX | Accumulator (operations) |
| BX | EBX | RBX | Base (addresses|data) |
| CX | ECX | RCX | Counter (loops, shifts) |
| DX | EDX | RDX | Data/Calculation Extensions |

Pointer and Index Registers

• Used for memory addressing.

Segment Registers (x86 real mode / legacy)

• Define memory regions.

Pointer Registers and EFLAGS

1. Pointer Registers

These registers are used for addressing and stack control. They point to important memory locations. An example is the address of arrays.

Main Pointers in x86

📌 Practical example:

• When a function is called, the return address is pushed onto the stack using SP/RSP.
• BP/RBP is use to access local variables.
• IP/EIP/RIP ensures that the CPU knows which instruction to execute next.

2. EFLAG'S (or FLAGS, RFLAGS in 64-bit)

This is a status and control register.

• It stores information about the results of ALU operations.
• It also controls certain processor execution modes.
• Each bit has a special meaning.

Main Flags

📌 Practical example in Assembly:

    mov eax, 5
    sub eax, 5 ; result = 0; Here the Zero Flag (ZF) will be activated in EFLAGS

x86 architecture

EAX(x86), AX, AH, AL - Used for input and output port accesses, arithmetic calls
EBX(x86), BX, BH, BL - Base register. Base for pointer accesses in memory
ECX(x86), CX, CH, CL - Counter register. Counter loops and shifts
EDX(x86), DX, DH, DL - Data register. Used for input and output, arithmetic, and some interrupted calls

Segment Registers – x86

Segment Registers are used by the x86 architecture to implement segmented memory addressing. They define the base of a memory segment, while other registers (such as EIP, ESP, etc.) provide the offset within that segment. The physical address is obtained by combining the segment value with the offset.

📌 List of Segment Registers

1. CS (Code Segment)

• Function: Stores the base address of the code segment.
• It is used to locate instructions that the processor should fetch and execute.
• It always works in conjunction with the IP/EIP/RIP (Instruction Pointer) register.
• It holds the code segments in which your program executes.

Example:

If `CS = 0x2000` and `EIP = 0x0010`, the next instruction is at `0x20000 + 0x10 = 0x20010`.

2. DS (Data Segment)

• Function: Stores the base address of the default data segment.
• Used to access global variables, arrays, buffers, etc.
• When an instruction accesses memory (e.g., MOV AX, [BX]), by default the processor uses DS as the base.
• Holds the data of the segment your program accesses

3. SS (Stack Segment)

• Function: Stores the base address of the stack.
• Works with SP/ESP/RSP (Stack Pointer).
• Used in operations such as PUSH, POP, function calls, and returns.
• Holds the stack segments your program uses.

Example:

If `SS = 0x3000` and `ESP = 0x00F0`, the top address of the stack is `0x30000 + 0xF0`.

4. ES (Extra Segment)

• Function: Extra segment for data.
• Used as an auxiliary register in memory block movement instructions (e.g., MOVS, LODS, STOS). - Usually appears in instructions that use DS:SI → ES:DI as source and destination.

5. FS and GS

• Function: Extra registers added in more modern processors.
• Used for:
• Access to special operating system structures.
• Quick access to local threads and internal structures (for example, in Windows, FS points to the Thread Information Block).
• Can also be used by compilers for optimizations.

📌 How they work together

• The processor always combines:
• A Segment Register (CS, DS, SS, ES, FS, GS)
• With an offset (IP, SP, BX, SI, etc.)
• General formula for the physical address in real mode (16 bits):

    ┌───────────────┐
    │   Segment Reg │
    │   (CS, DS,   │
    │    SS, ES)   │
    └──────┬────────┘
           │
           ▼
      Segment base
           │
           ▼
  ┌───────────────────┐
  │   Offset          │
  │  segment          │
  │ (IP, SP, BP, SI…) │
  └─────────┬─────────┘
            │
            ▼
    Physic adress from memory

Explanation:

• Segment Register → Defines the beginning of the segment.
• Offset → Position within the segment.
• Physical Address → Segment × 16 + Offset.

Example:

CS = 0x2000
IP = 0x0010

Physical Address = 0x2000 * 16 + 0x10 = 0x20010

• This helped the processor access large areas of memory using 16-bit registers.
  The use of segments allowed for the separation of different types of data (CS, DS, SS, ES...)

Why do Segment Registers exist?

1. Addressing Limitation in Early x86s

• The first x86 processors (8086) were 16-bit, meaning they could use only 16 bits to directly address memory.

• With 16 bits, you could only address 2¹⁶ = 65,536 bytes (64 KB).

• But programs needed to access more memory (up to 1 MB on the 8086).

• Solution: Segmented addressing, using:

• Segment (16 bits) → defines the 64 KB block/base

• Offset (16 bits) → position within the block

• In modern processors (32/64 bits), we use a flat memory model:

Index and Pointer Registers – x86

In the x86 architecture, in addition to general registers, there are registers used primarily for memory addressing:

• Pointer Registers → point to specific addresses in memory (e.g., stack, database).
• Index Registers → used to navigate within arrays, tables, or strings.

1. Pointer Registers

Practical example:

    push ax; decrements SP and writes AX to the top of the stack
    mov ax, [bp+4]; accesses a local variable on the stack using BP as the base

1. CR0 – Control Register 0

• 32- or 64-bit register depending on the processor.
• Controls CPU operating mode and some basic protections.

Important bits of CR0:

Function Summary:

• Enables protected mode
• Controls FPU
• Sets write protections
• Enables paging (virtual memory)

2. CR4 – Control Register 4

• Additional register for advanced processor features.
• Each bit enables a specific feature.

Important bits of CR4:

Function Summary:

• Enables extended physical addressing
• Enables hardware error checking
• Configures advanced support for SSE and SIMD
• Optimizes TLB management and paging

🔑 Quick Summary