📘 CPU Architecture and Assembly Language Guide

🔹 What are Registers?

• Registers are small storage areas inside the CPU.
• They are significantly faster than RAM and are used for immediate calculations, addresses, control, and flags.
• Each architecture defines:
  • The number of available registers.
  • Their size (8, 16, 32, 64 bits, etc.).
  • The specific function of each.

🔹 x86 Architecture (32-bit)

Main general-purpose registers (32 bits each):

Other important registers:

• EIP → Instruction Pointer (address of the next instruction).
• EFLAGS → Flags register (carry, zero, sign, overflow, etc.).

🔹 x86-64 Architecture (64-bit)

• Expansion of registers from 32 to 64 bits.
• Prefix changes from E → R (e.g., EAX → RAX).

Extras:

• R8–R15 → Additional general-purpose registers for increased flexibility.
• RIP → Instruction Pointer (64-bit).

🔹 ARM Architecture (ARMv7 – 32-bit)

ARM uses a set of 16 registers of 32 bits:

🔹 ARM64 Architecture (AArch64)

The 64-bit version of ARM features 31 general-purpose registers:

🔹 General Summary

• Registers = ultra-fast memory inside the CPU.
• Each architecture has its own set of registers and conventions.
• Primary uses:
  • Arithmetic and logic (EAX/RAX, R0–R3, X0–X7).
  • Loop counting (ECX/RCX).
  • Stack management and function calls (ESP/RSP, SP, FP, LR).
  • Execution control (EIP/RIP, PC).

🔹 Notation: reg32, reg16, reg8

In Assembly, registers can be accessed in different sizes. The notation reg32, reg16, and reg8 indicates how many bits of the register are being used.

1. reg32 (32 bits)

• Uses the entire 32-bit register.
• Examples: EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP.
• Function: Full 32-bit integer operations.

Example:

    mov eax, 0x12345678   ; Loads full 32 bits into EAX
    add ebx, eax          ; Adds the 32-bit value of EAX to EBX

🔹 Assembly Notations: <mem>, <con32>, <con16>, <con8>, <con>

In Assembly manuals, you will see placeholders representing the types of operands an instruction can accept.

1. <mem> – Memory

• Represents any memory address.
• Can be a byte, word (16 bits), or dword (32 bits), depending on the instruction.

Example:

    mov eax, [ebx]     ; Reads 32 bits from memory pointed to by EBX
    mov al, [esi+4]    ; Reads 8 bits from memory at address ESI+4

2. Constants (Immediates)

• <con32>: 32-bit literal constant (e.g., 0x12345678).
• <con16>: 16-bit literal constant (e.g., 0xABCD).
• <con8>: 8-bit literal constant (e.g., 0xFF).
• <con>: Generic constant whose size depends on the context (e.g., mov eax, 5 uses a 32-bit constant).

Summary Table of Notations

🔹 Common Assembly Instructions

MOV (Move)

The MOV instruction copies a value from a source to a destination. Note: It does not actually "move" (delete) the source; it performs a copy.

    mov DESTINATION, SOURCE

• Destination and source must be the same size.
• Cannot perform memory-to-memory moves directly (must use a register as an intermediary).

Examples:

    mov eax, 1234h     ; Places 0x1234 in EAX
    mov edx, eax       ; Copies value from EAX to EDX
    mov eax, [var]     ; Loads value from memory "var" into EAX
    mov [var], 1234h   ; Saves immediate value 0x1234 to memory "var"

ADD (Addition)

Sums two values and stores the result in the first operand.

Examples:

    add eax, ebx       ; eax = eax + ebx
    add eax, 5         ; eax = eax + 5

🔹 Glossary of Common Instructions

🔹 Word, Dword, and Qword Quantifiers

In x86, these terms define specific data sizes:

Note: In other architectures like ARM, a "word" often refers to 32 bits.

🔹 x86 Register Evolution

🔹 EFLAGS Register (Status and Control)

The EFLAGS register (RFLAGS in 64-bit) stores the status of CPU operations.

🔹 Segment Registers (x86)

Used for segmented memory addressing. In modern 32/64-bit systems, a "flat memory model" is typically used, but these registers still exist for compatibility and specific OS tasks.

Physical Address Calculation (Real Mode):
Physical Address = (Segment * 16) + Offset

🔹 Control Registers (CR0, CR4)

These registers control the fundamental behavior of the CPU.

CR0 - Control Register 0

• PE (Protection Enable): Enables Protected Mode.
• WP (Write Protect): Prevents supervisor-level writes to read-only pages.
• PG (Paging): Enables Virtual Memory paging.

CR4 - Control Register 4

• PAE (Physical Address Extension): Allows addressing more than 4GB of physical RAM on 32-bit systems.
• MCE (Machine Check Enable): Enables hardware error reporting.
• OSFXSR: Enables SSE (Streaming SIMD Extensions) support.

🔑 Quick Summary