Advanced Bit Manipulation Instructions: A Deep Dive for Systems Professionals

1) Introduction and Scope

This study guide provides an in-depth technical exploration of bit manipulation instructions available in various processor architectures. Unlike software implementations that often require multiple instructions to achieve bitwise operations, hardware-level bit manipulation instructions offer significant performance advantages. This guide aims to equip cybersecurity professionals, embedded systems engineers, and computer architects with a foundational understanding of these instructions, their architectural nuances, practical applications, and defensive implications. We will delve into the underlying mechanics, explore concrete examples, and highlight common pitfalls and mitigation strategies.

The scope of this guide encompasses:

• Architectural Overview: Examining the presence and evolution of bit manipulation instructions across prominent CPU architectures (x86, ARM, Power ISA, RISC-V, legacy systems).
• Instructional Deep Dive: Analyzing specific instructions, their operands, and their effects on processor state (registers, flags).
• Practical Applications: Demonstrating how these instructions are utilized in real-world scenarios, including low-level I/O, cryptography, and data processing.
• Performance and Security Implications: Discussing the performance benefits and potential security considerations associated with hardware bit manipulation.

2) Deep Technical Foundations

Bit manipulation instructions operate directly on the binary representation of data within registers or memory. These operations are fundamental to computer science and are critical for tasks such as:

• Flag Management: Setting, clearing, testing, and toggling individual bits within status or control registers. This is foundational for conditional logic and state tracking.
• Data Packing and Unpacking: Efficiently extracting or inserting specific fields from larger data structures, crucial for optimizing memory usage and data transfer.
• Masking and Filtering: Isolating or modifying subsets of bits. This is extensively used in hardware interfaces, data validation, and protocol parsing.
• Bitwise Logic: Performing AND, OR, XOR, NOT operations at the bit level. These are the building blocks for many algorithms and data transformations.
• Counting and Shifting: Determining the number of set bits (population count), leading/trailing zeros, or rearranging bit sequences via shifts and rotates. These are vital for compression, error detection/correction codes, and certain mathematical operations.
• Specialized Operations: Cryptographic primitives (e.g., S-boxes, diffusion layers), Galois Field arithmetic (essential for error correction codes like Reed-Solomon and cryptography like AES), and bit-matrix operations.

The efficiency of these instructions stems from their direct mapping to hardware logic gates, enabling operations that would otherwise require complex sequences of software instructions, thereby reducing instruction count, clock cycles, and power consumption.

3) Internal Mechanics / Architecture Details

3.1) Instruction Categories and Operands

Bit manipulation instructions can be broadly categorized based on their functional behavior:

• Bitwise Logic Operations: These instructions perform logical operations on corresponding bits of two operands.

  • AND: Result bit is 1 if both operand bits are 1.

  • OR: Result bit is 1 if either operand bit is 1.

  • XOR: Result bit is 1 if the operand bits are different.

  • NOT (or Complement): Inverts each bit of a single operand.

  • NAND, NOR: Variations of AND/OR with inverted output.

  • Example (x86 Assembly):

    MOV EAX, 0b11001010  ; EAX = 202 (decimal)
    MOV EBX, 0b10101100  ; EBX = 172 (decimal)
    
    AND EAX, EBX         ; EAX = 0b10001000 (136 decimal)
    ; EAX = 0b11001010 & 0b10101100 = 0b10001000
    
    MOV EAX, 0b11001010
    OR EAX, EBX          ; EAX = 0b11101110 (238 decimal)
    ; EAX = 0b11001010 | 0b10101100 = 0b11101110
    
    MOV EAX, 0b11001010
    XOR EAX, EBX         ; EAX = 0b01100110 (102 decimal)
    ; EAX = 0b11001010 ^ 0b10101100 = 0b01100110
    
    MOV EAX, 0b11001010
    NOT EAX              ; EAX = 0b...111100110101 (assuming 32-bit register)
    ; EAX = ~0b11001010

• Bit Test/Set/Clear/Toggle: Operations targeting a single bit at a specific index within a register or memory location. These often use a mask (e.g., 1 << bit_index).

  • Example (Conceptual Pseudocode):

    // Test bit at index N in REGISTER
    // Flags: ZF (Zero Flag) is set if the result of the AND is zero.
    IF (REGISTER & (1 << N)) == 0 THEN
        // Bit N is CLEAR (0)
    ELSE
        // Bit N is SET (1)
    END IF
    
    // Set bit at index N in REGISTER
    REGISTER = REGISTER | (1 << N)
    
    // Clear bit at index N in REGISTER
    // Use bitwise NOT to create a mask with 0 at bit N and 1s elsewhere.
    REGISTER = REGISTER & ~(1 << N)
    
    // Toggle bit at index N in REGISTER
    REGISTER = REGISTER ^ (1 << N)

• Bit Scan Instructions: Find the index of the first set bit.

  • BSR (Bit Scan Reverse - x86): Finds the index of the most significant set bit. Operates on a 16, 32, or 64-bit operand. If the operand is zero, the Zero Flag (ZF) is set, and the destination register is undefined.

  • BSF (Bit Scan Forward - x86): Finds the index of the least significant set bit. Operates on a 16, 32, or 64-bit operand. If the operand is zero, ZF is set, and the destination register is undefined.

  • Example (x86 Assembly):

    MOV EAX, 0x00000018   ; EAX = 0b00011000 (decimal 24)
    BSF EBX, EAX          ; EBX = 3 (index of LSB set bit)
    ; EAX = 0b00011000, LSB set bit is at index 3 (0-indexed from right)
    
    MOV EAX, 0x00000018
    BSR ECX, EAX          ; ECX = 4 (index of MSB set bit)
    ; EAX = 0b00011000, MSB set bit is at index 4
    
    MOV EAX, 0            ; EAX = 0
    BSF EBX, EAX          ; ZF is set, EBX is undefined.

• Count Leading/Trailing Zeros:

  • LZCNT (Count Leading Zeros - x86 BMI1): Counts the number of zero bits from the most significant bit down to the first set bit. If the operand is zero, the result is the operand size (e.g., 32 for a 32-bit register).

  • TZCNT (Count Trailing Zeros - x86 BMI1): Counts the number of zero bits from the least significant bit up to the first set bit. If the operand is zero, the result is the operand size.

  • Example (x86 Assembly):

    MOV EAX, 0b000010100000  ; EAX = 160 (decimal), assume 32-bit register
    LZCNT EBX, EAX           ; EBX = 26 (32 - 6 - 0 = 26 leading zeros)
    ; Binary representation (32-bit): 0000...000010100000
    
    MOV EAX, 0b000010100000
    TZCNT ECX, EAX           ; ECX = 5 (number of trailing zeros before the first '1')
    ; Binary representation: ...10100000
    
    MOV EAX, 0
    LZCNT EBX, EAX           ; EBX = 32 (for 32-bit operand)
    TZCNT ECX, EAX           ; ECX = 32 (for 32-bit operand)

• Population Count (Popcount): Counts the total number of set bits (1s) in a value.

  • POPCNT (x86 SSE4.2/BMI1): Efficiently counts set bits.

  • Example (x86 Assembly):

    MOV EAX, 0b10110101  ; EAX = 181 (decimal), assume 8-bit for clarity
    POPCNT EBX, EAX      ; EBX = 5 (number of set bits)

• Bit Extract/Deposit: These instructions allow for sophisticated manipulation of contiguous bit fields.

  • PEXT (Parallel Bit Extract - x86 BMI2): Extracts bits from a source operand based on a mask, placing them contiguously in the destination. The mask determines which bits to extract.

  • PDEP (Parallel Bit Deposit - x86 BMI2): Deposits bits from a source operand into a destination based on a mask. The mask determines where the bits from the source are placed contiguously.

  • Example (x86 Assembly):
    Let SRC = 0b11010110 (binary), MASK = 0b10101010 (binary).

    MOV EAX, 0b11010110  ; Source data
    MOV EBX, 0b10101010  ; Mask
    
    ; PEXT: Extract bits from EAX where EBX has a 1.
    ; Bits in EAX at mask positions (from right to left): 0, 1, 0, 1, 0, 1.
    ; PEXT places these extracted bits contiguously.
    PEXT ECX, EAX, EBX   ; ECX = 0b00000101 (decimal 5)
    ; The extracted bits are 0, 1, 0, 1, 0, 1. PEXT aligns them to LSB.
    ; The result is 0b0101.
    
    MOV EAX, 0b11010110  ; Source data
    MOV EBX, 0b10101010  ; Mask
    
    ; PDEP: Deposit bits from EAX into ECX based on EBX mask.
    ; The bits from EAX (11010110) are placed into ECX at positions where EBX is 1.
    ; EAX bits used contiguously: 1, 1, 0, 1, 0, 1, 1, 0
    ; Mask positions (from right to left): 0, 1, 0, 1, 0, 1, 0, 1
    ; Bit 0 (from EAX): 1 -> goes to mask bit 0 (pos 1)
    ; Bit 1 (from EAX): 1 -> goes to mask bit 1 (pos 3)
    ; Bit 2 (from EAX): 0 -> goes to mask bit 2 (pos 5)
    ; Bit 3 (from EAX): 1 -> goes to mask bit 3 (pos 7)
    ; ... and so on.
    PDEP EDX, EAX, EBX   ; EDX = 0b10101010 (decimal 170)
    ; EAX = 0b11010110
    ; EBX = 0b10101010
    ; PDEP places bits from EAX into positions indicated by EBX.
    ; The LSB of EAX (0) goes to the first set bit in EBX (position 1).
    ; The next bit of EAX (1) goes to the next set bit in EBX (position 3).
    ; Result: 0b10101010 (if EAX has enough bits to fill the mask)
    ; Correct interpretation: EAX bits are consumed sequentially.
    ; EAX = 11010110. EBX = 10101010.
    ; Bit 0 of EAX (0) goes to position 1 of result (where EBX has 1).
    ; Bit 1 of EAX (1) goes to position 3 of result.
    ; Bit 2 of EAX (1) goes to position 5 of result.
    ; Bit 3 of EAX (0) goes to position 7 of result.
    ; Result: 0b01010100 (decimal 84)
    ; Let's re-verify PDEP logic:
    ; EAX=0b11010110, EBX=0b10101010
    ; Bits from EAX: 0, 1, 1, 0, 1, 0, 1, 1 (LSB first)
    ; Mask bits:     1, 0, 1, 0, 1, 0, 1, 0 (LSB first)
    ; Pos 0 (mask 0): skip
    ; Pos 1 (mask 1): take EAX bit 0 (0) -> result bit 1 = 0
    ; Pos 2 (mask 0): skip
    ; Pos 3 (mask 1): take EAX bit 1 (1) -> result bit 3 = 1
    ; Pos 4 (mask 0): skip
    ; Pos 5 (mask 1): take EAX bit 2 (1) -> result bit 5 = 1
    ; Pos 6 (mask 0): skip
    ; Pos 7 (mask 1): take EAX bit 3 (0) -> result bit 7 = 0
    ; Result: 0b000001010100 (if we consider 8 bits from EAX)
    ; For 8-bit EAX and EBX:
    ; EAX = 0b11010110
    ; EBX = 0b10101010
    ; PDEP EDX, EAX, EBX
    ; EDX will be 0b01010100

• Bit Permutation/Shuffle: Rearranging bits within a register according to a control mask or index.

  • VPSHUFBITQMB (AVX-512): Selects bits from one source operand based on indices provided in a second operand. This is powerful for arbitrary bit reordering.
  • PDEP/PEXT can also be used in combination to achieve complex permutations.

• Ternary Logic: Performing a logical operation based on three operands, often used for complex bitwise functions and control flow.

  • VPTERNLOG (AVX-512): Performs a bitwise ternary logic operation, defined by a 3-bit control vector. result = (a & b & c) | (~a & ~b & c) | (a & ~b & ~c) | ...

• Bit Matrix Operations: Specialized instructions for operations like matrix transposition or Galois Field arithmetic.

  • GF2P8AFFINEQB (AVX-512 GFNI): Performs an 8x8 bit-matrix multiply in GF(2^8), crucial for accelerating AES encryption/decryption.
  • VGbbd (Power ISA): Performs an 8x8 bit-matrix transpose.

3.2) Processor-Specific Implementations

• x86 (Intel/AMD):

  • Base Set: AND, OR, XOR, NOT, TEST (checks bits without modifying operands, sets flags), BT (Bit Test), BTS (Bit Test and Set), BTR (Bit Test and Reset), BTC (Bit Test and Complement).
  • SSE4/BMI1/BMI2: LZCNT, TZCNT, POPCNT, PEXT, PDEP. These significantly boost performance for common bitwise tasks.
  • AVX-512: Introduces highly specialized instructions like VPTERNLOG, VPCONFLICTD, VPSHUFBITQMB, GF2P8AFFINEQB, and others for advanced bit manipulation, vector processing, and cryptographic acceleration.
  • Flags: Many bit manipulation instructions affect the Zero Flag (ZF), Carry Flag (CF), Sign Flag (SF), and Overflow Flag (OF). For instance, AND, OR, XOR update ZF, SF, CF, OF based on the result. TEST updates these flags without altering operands. BSR/BSF update ZF based on whether the input was zero.

• ARM:

  • ARMv7-A (Cortex-A): Instructions like SETEND (Set Endianness), REV (Reverse Bytes), RBIT (Reverse Bits), bit-field instructions (SBFX, UBFX for extract; BFX for extract/insert).
  • ARMv8-A (A64): Expands on bit manipulation with instructions like RBIT, CLZ (Count Leading Zeros), CLS (Count Leading Sign bits), REV16, REV32, REV64. Vector extensions (NEON) provide SIMD bitwise operations.
  • Example (ARM Assembly - A64):

    MOV X0, #0b11001010  ; X0 = 202
    MOV X1, #0b10101100  ; X1 = 172
    
    AND X0, X0, X1       ; X0 = X0 & X1 = 0b10001000 (136)
    ORR X0, X0, X1       ; X0 = X0 | X1 = 0b11101110 (238)
    EOR X0, X0, X1       ; X0 = X0 ^ X1 = 0b01100110 (102)
    
    ; Clear bit 5 (0-indexed) of X0
    BIC X0, X0, #(1 << 5) ; X0 = X0 & ~(1 << 5)
    
    ; Set bit 3 of X0
    ORR X0, X0, #(1 << 3) ; X0 = X0 | (1 << 3)
    
    ; Test bit 7 of X0 and set Z flag if clear
    TST X0, #(1 << 7)    ; Sets flags based on X0 & (1 << 7)

• Power ISA:

  • Features a rich set of bit manipulation instructions, often with byte-level granularity and explicit control.
  • Includes CLZ (Count Leading Zeros), CTZ (Count Trailing Zeros), POPCNTB (Population Count Byte), POPCNTW (Word), POPCNTD (Doubleword).
  • PEXTD (Parallel Bit Extract Doubleword), PDEPd (Parallel Bit Deposit Doubleword) are analogous to x86 BMI2.
  • BPERMD (Bit Permute Doubleword) allows arbitrary bit reordering.
  • XXEVAL (Ternary Logic) for complex bitwise operations.

• RISC-V:

  • Base ISA: AND, OR, XOR, ANDN (AND NOT), ORN (OR NOT), XNOR.
  • 'B' Extension (Bit Manipulation): Provides CLZ, CTZ, PCNT (Population Count), BSET (Set bit), BCLR (Clear bit), BINV (Invert bit), BEXT (Extract bit), ROR (Rotate Right), RORI (Rotate Right Immediate).
  • RVV (Vector Extension): Supports vector masks and operations like vpopcnt (Vector Population Count) for parallel bit processing.
  • Example (RISC-V Assembly - RV32I 'B' extension):

    li a0, 0b11001010   ; a0 = 202
    li a1, 0b10101100   ; a1 = 172
    
    and a0, a0, a1      ; a0 = a0 & a1 = 0b10001000 (136)
    or a0, a0, a1       ; a0 = a0 | a1 = 0b11101110 (238)
    xor a0, a0, a1      ; a0 = a0 ^ a1 = 0b01100110 (102)
    
    ; Clear bit 5 of a0
    bclri a0, 5         ; a0 = a0 & ~(1 << 5)
    
    ; Set bit 3 of a0
    bseti a0, 3         ; a0 = a0 | (1 << 3)
    
    ; Count leading zeros in a0 (32-bit)
    clz a1, a0          ; a1 = count of leading zeros in a0
    
    ; Count trailing zeros in a0
    ctz a1, a0          ; a1 = count of trailing zeros in a0
    
    ; Population count of a0
    pcnt a1, a0         ; a1 = number of set bits in a0

• Legacy Architectures (e.g., 8051, Z80, 6502):

  • Often feature simpler bit manipulation instructions crucial for their limited capabilities and resource constraints.
  • 8051 (8-bit): SETB (Set Bit in Register/Memory), CLR (Clear Bit), CPL (Complement Bit), ANL (AND Logical with Accumulator), ORL (OR Logical with Accumulator). These operate on individual bits within registers (like ACC.0 to ACC.7) or specific bit-addressable memory locations.
    • Example (8051 Assembly):

      SETB P1.2   ; Set bit 2 of Port 1
      CLR P1.0    ; Clear bit 0 of Port 1
      CPL P1.3    ; Complement bit 3 of Port 1

  • Z80: BIT (Test Bit and set Z flag), RES (Reset Bit), SET (Set Bit). These operate on any bit of any 8-bit register or memory location.
    • Example (Z80 Assembly):

      BIT 7, A    ; Test bit 7 of Accumulator A. Sets Z flag if bit is 0.
      RES 3, B    ; Reset bit 3 of Register B.
      SET 5, (HL) ; Set bit 5 of memory location pointed to by HL.

  • WDC 65C02: TSB (Test and Set Bit - sets bit and clears Z flag if bit was 0), TRB (Test and Reset Bit - clears bit and clears Z flag if bit was 1). These are atomic operations.

3.3) Memory Layout and Bit Access

When performing bit manipulation on memory, understanding the byte ordering (endianness) and memory addressing is critical. Instructions that operate directly on bits within memory locations (e.g., SETB/CLR in 8051, BIT/RES/SET in Z80) abstract away much of this complexity. However, for more general-purpose instructions like AND, OR, XOR on memory, you typically load a byte/word, manipulate it in a register, and then store it back.

Example: Memory Bit Access (Conceptual x86)

Consider a byte in memory at address 0x2000: 0xAB (binary 10101011).
We want to set bit 3 (0-indexed from LSB).

; x86 Assembly
MOV EAX, DWORD PTR [0x2000] ; Load the byte into the lower byte of EAX. EAX = 0x000000AB
MOV CL, 3                   ; Bit index to set

; Option 1: Using bitwise OR with a mask
; Create mask: 1 << CL
MOV EBX, 1
SHL EBX, CL                 ; EBX = 0x08 (binary 00001000)
OR EAX, EBX                 ; EAX = 0x000000AB | 0x00000008 = 0x000000AB (bit 3 was already set)
                            ; If EAX was 0x000000A3 (10100011), it would become 0x000000AB (10101011)

; Option 2: Using BSF/BSR (less direct for set/clear, more for testing/finding)
; For direct set/clear on memory, specific instructions or load-modify-store are used.

MOV DWORD PTR [0x2000], EAX ; Store the modified byte back to memory.

More advanced instructions like PDEP/PEXT operate on registers. If you need to perform these on memory, you'd typically load a contiguous block of memory into a register, perform the operation, and then store it back. Atomic operations are crucial when multiple threads or cores might access the same memory location.

4) Practical Technical Examples

4.1) Low-Level I/O and Embedded Systems

Bit manipulation instructions are indispensable for direct hardware control in embedded systems and device drivers.

Scenario: Controlling specific bits of a peripheral's status or control register.
Assume a hypothetical memory-mapped I/O register STATUS_REG at address 0x40001000.
Bit 0: DATA_READY flag
Bit 1: ERROR_FLAG
Bit 2: TRANSMIT_ENABLE control bit

// C code for embedded system / device driver
volatile uint32_t *STATUS_REG = (volatile uint32_t *)0x40001000;

#define DATA_READY_MASK (1 << 0)
#define ERROR_FLAG_MASK (1 << 1)
#define TRANSMIT_ENABLE_MASK (1 << 2)

void enable_transmitter() {
    // Atomically set the TRANSMIT_ENABLE bit
    // On architectures with atomic bit set instructions, this is a single instruction.
    // Example (conceptual): SET_BIT(STATUS_REG, 2);
    // Software equivalent:
    *STATUS_REG |= TRANSMIT_ENABLE_MASK;
}

void disable_transmitter() {
    // Atomically clear the TRANSMIT_ENABLE bit
    // Example (conceptual): CLR_BIT(STATUS_REG, 2);
    // Software equivalent:
    *STATUS_REG &= ~TRANSMIT_ENABLE_MASK;
}

bool is_data_ready() {
    // Atomically test the DATA_READY bit
    // Example (conceptual): TEST_BIT(STATUS_REG, 0);
    // Software equivalent:
    return (*STATUS_REG & DATA_READY_MASK) != 0;
}

bool has_error() {
    // Atomically test the ERROR_FLAG bit
    return (*STATUS_REG & ERROR_FLAG_MASK) != 0;
}

In architectures like the 8051 or Z80, enable_transmitter and disable_transmitter would map to single, atomic instructions (SETB Px.y, CLR Px.y, SET y, (reg), RES y, (reg)), significantly improving efficiency and atomicity compared to the C code's load-modify-store sequence.

4.2) Cryptographic Operations

Bit manipulation is fundamental to many cryptographic algorithms.

Scenario: Implementing a bit-level permutation for a block cipher.
Consider a simplified permutation that swaps nibbles (4-bit groups) within a byte.
Input byte: 0b1101_0110 (MSN=1101, LSN=0110)
Desired output: 0b0110_1101 (LSN becomes MSN, MSN becomes LSN)

Using x86 PEXT/PDEP:
Let data = 0b11010110.
We want to extract the lower nibble and the upper nibble and swap them.

; Assume data is in EAX
MOV EAX, 0b11010110

; Mask for lower nibble: 0x0F (0b00001111)
MOV EBX, 0x0F
; Mask for upper nibble: 0xF0 (0b11110000)
MOV ECX, 0xF0

; Extract lower nibble (0110)
PEXT EDX, EAX, EBX      ; EDX = 0b0110 (after extraction and alignment)

; Extract upper nibble (1101)
PEXT ESI, EAX, ECX      ; ESI = 0b1101 (after extraction and alignment)

; Now, deposit ESI (upper nibble) into the lower nibble position of a new register
; and EDX (lower nibble) into the upper nibble position.
; We need a mask for depositing into the upper nibble (0xF0) and lower nibble (0x0F).
MOV EDI, 0x0F           ; Mask for depositing into lower nibble position
MOV EBP, 0xF0           ; Mask for depositing into upper nibble position

; Deposit ESI (1101) into the lower nibble position (mask 0x0F)
PDEP EAX, ESI, EDI      ; EAX = 0b00001101

; Deposit EDX (0110) into the upper nibble position (mask 0xF0)
PDEP EBX, EDX, EBP      ; EBX = 0b01100000

; Combine the two parts
OR EAX, EBX             ; EAX = 0b00001101 | 0b01100000 = 0b01101101
                        ; This is the desired swapped nibble result.

Software Fallback (Conceptual Python):

data = 0b11010110
lower_nibble = data & 0x0F       # 0b0110
upper_nibble = (data >> 4) & 0x0F # 0b1101

swapped_data = (lower_nibble << 4) | upper_nibble
print(f"{swapped_data:08b}") # Output: 01101101

The PEXT/PDEP approach can be more efficient, especially when dealing with larger data widths or more complex permutations.

4.3) Data Structure Manipulation and Bit Fields

Efficiently manipulating packed data structures is a common use case.

Scenario: Extracting a 7-bit field from a 64-bit integer, starting at bit offset 12.
Let data = 0x123456789ABCDEF0 (64-bit). We want bits 12 through 18.

Using x86 PEXT (BMI2):
The field starts at bit 12 and has a length of 7 bits.
The mask needs to have 7 bits set, starting at the correct position.
The mask is (1 << 7) - 1 shifted left by 12.
Mask = (0x7F) << 12 = 0b1111111 << 12 = 0b1111111000000000000 (hex 0x00000000007F8000).

; Assume data is in RAX (64-bit register)
MOV RAX, 0x123456789ABCDEF0

; Mask for the 7-bit field starting at bit 12
MOV RDI, 0x00000000007F8000

; PEXT instruction (BMI2)
PEXT RBX, RAX, RDI      ; RBX will contain the extracted 7 bits, aligned to LSB.

; Let's trace:
; RAX = 0x123456789ABCDEF0
; Binary (last few bytes): ... 1010 1011 1100 1101 1110 1111 1111 0000
; Bit 12 is the 13th bit from the right.
; Bits 12-18 are: 0001101 (from ...1010 1011 1100 1101 1110 1111 1111 0000)
; The bits at positions 12, 13, 14, 15, 16, 17, 18 are: 1, 0, 1, 1, 1, 1, 1.
; Wait, the example data is: 0x123456789ABCDEF0
; ... 1010 1011 1100 1101 1110 1111 1111 0000
; Bit 0: 0
; Bit 1: 0
; Bit 2: 0
; Bit 3: 1
; Bit 4:

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## Source

- Wikipedia page: https://en.wikipedia.org/wiki/Bit_manipulation_instructions
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- AI enriched at: 2026-03-30T20:14:24.834Z